Karthik B K

Karthik B K

CPU Design Engineer / Micro-Architect

Education

  • Indian Institute of Technology Madras
    Master of Science by Research, Electrical Engineering
    2025 - Present
  • PES University
    Bachelor of Technology, Electronics and Communication Engineering
    2018 - 2022

Publications

  • Suroshi, V., Karthik, B. K., Kannur, V., Reddy, V., & Purnaprajna, M. (2025).
    Optimization of sub-threshold standard cells for energy efficient designs.
    38th International Conference on VLSI Design (VLSID).

Work Experience

  • CPU Design Engineer / Micro-Architect
    InCore Semiconductors | Jan 2022 - Present

    I worked on various exciting things at InCore. All the way from core micro-arch to application profiling and secure-boot. Most of it has been uArch for Calcite, mostly frontend, especially instruction fetch and physical memory protection. I was directly supervised by Neel Gala.

Research Experience

  • Research Intern
    Centre for Heterogeneous and Intelligent Processing Systems | Jan 2021 - Dec 2021
    Advisor: Madhura Purnaprajna
    • Studied the effects of supply voltage scaling on power and performance of standard cells.
    • Designed and simulated a sub-threshold standard cells to optimize energy efficiency.
    • Teaching Assistant for the EDA class of 2021.
    • UMC 55nm Commercial Process Node

References

  • Neel Gala
    CTO / Co-Founder, InCore Semiconductors
    neelgala@incoresemi.com
  • Nitin Chandrachoodan
    Professor, Integrated Circuits and Systems (ICS)
    Indian Institute of Technology Madras
    nitin@ee.iitm.ac.in
  • Madhura Purnaprajna
    Professor, Centre for Heterogeneous and Intelligent Processing Systems (CHIPS)
    PES University
    madhurap@pes.edu
  • Boris Grot
    Professor, Edinburgh Architecture and Systems Lab (EASE)
    University of Edinburgh
    boris.grot@ed.ac.uk

Projects

  • RISC-V Application Profiler
    Duration: Jun 2023 - Sep 2023
    Mentor. Secondary Contributor. [Code]
  • Energy Efficient Sub-Threshold Standard Cells
    Duration: Oct 2020 - Dec 2021
    Bachelor's thesis project. Primary Contributor. [Docs]
  • uATG tests for a Non-Coherent Cache Subsystem (Chromite)
    Duration: Jun 2020 - Nov 2021
    Course project. Co-contributor. [Code]

Articles & Blogs

  • Exploring the hidden wonders: CPU Micro-Architecture
    Medium | June 2023
    A short article on CPU Micro-Architecture.
    [Read Here]
  • RISC-V Memory Protection: Diving Deep into the Complexities
    Medium | Nov 2023
    A short article on RISC-V Physical Memory Protection.
    [Read Here]

Workshops

  • FPGA Summer School (2024)
    PES University
    Attendee.
  • EFCL Summer School (2024)
    ETH Zurich
    Attendee.
  • Computer Architecture Winter School (2021)
    PES University, IIT Madras
    Attendee.

Awards & Recognition

  • Chairperson's list of top ten performers (2022)
    D-ECE, PES University
    Recieved the chairperson's award for top scorers with consistent academic performance and demonstrating an exemplary commitment to learning.